Verilog

Verilog is a hardware description language created in 1984.

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Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits, as well as in the design of genetic circuits.. Read more on Wikipedia...

Verilog Wikipedia page
Verilog docs
There are at least 48,035 Verilog repos on GitHub
PLDB estimates there are currently 246 job openings for Verilog programmers.
file extensions for Verilog include v and veo
The Google BigQuery Public Dataset GitHub snapshot shows 2k users using Verilog in 3k repos on GitHub
There are 2,421 members in the Verilog subreddit
Explore Verilog snippets on Rosetta Code
Verilog on HOPL
Verilog ranks #50 in the TIOBE Index
Verilog Ubuntu package
ANTLR grammar for Verilog
CodeMirror package for syntax highlighting Verilog
Pygments supports syntax highlighting for Verilog
GitHub supports syntax highlighting for Verilog
Verilog appears in the Quine Relay project
Indeed.com has 246 matches for "verilog developer".
See also: (5 related languages)SystemVerilog, C, VHDL, OpenVera, Property Specification Language
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Example from Riju:

module main;

initial begin
  $display("Hello, world!");
end

endmodule

Example from hello-world:

module main;
  initial
    begin
      $display("Hello World");
      $finish;
    end
endmodule

Example from the Hello World Collection:

/* Hello World in Verilog. */

module main;

 initial
   begin
     $display("Hello, World");
     $finish ;
   end

 endmodule

Example from Linguist:

`timescale 1ns / 1ps
// Copyright (C) 2008 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
module mux(opA,opB,sum,dsp_sel,out);
	input [3:0] opA,opB;
	input [4:0] sum;
	input [1:0] dsp_sel;
	output [3:0] out;
	
	reg cout;
	
	always @ (sum)
		begin
			if (sum[4] == 1)
				cout <= 4'b0001;
			else
				cout <= 4'b0000;
		end
	
	reg out;
	
	always @(dsp_sel,sum,cout,opB,opA)
		begin
			if (dsp_sel == 2'b00)
				out <= sum[3:0];
			else if (dsp_sel == 2'b01)
				out <= cout;
			else if (dsp_sel == 2'b10)
				out <= opB;
			else if (dsp_sel == 2'b11)
				out <= opA;
		end

endmodule

Example from Wikipedia:

initial
  a = 0;

initial
  b = a;

initial
  begin
    #1;
    $display("Value a=%d Value of b=%d",a,b);
  end

Keywords in Verilog

always assign automatic begin case casex casez cell config deassign default defparam design disable edge else end endcase endconfig endfunction endgenerate endmodule endprimitive endspecify endtable endtask event for force forever fork function generate genvar if ifnone incdir include initial inout input instance join liblist library localparam macromodule module negedge noshowcancelled output parameter posedge primitive pulsestyleondetect pulsestyleonevent reg release repeat scalared showcancelled signed specify specparam strength table task tri tri0 tri1 triand wand trior wor trireg unsigned use vectored wait while wire

Feature	Supported	Token	Example
Binary Literals	✓		// ([0-9]+)\|(\'b)[01]+
Integers	✓		// ([0-9]+)\|(\'d)[0-9]+
Floats	✓		// (\d+\.\d*\|\.\d+\|\d+)[eE][+-]?\d+[lL]?
Hexadecimals	✓		// ([0-9]+)\|(\'h)[0-9a-fA-F]+
Octals	✓		// ([0-9]+)\|(\'o)[0-7]+
Conditionals	✓
Functions	✓
While Loops	✓
Case Sensitivity	✓
Strings	✓	"	"Hello world"
MultiLine Comments	✓	/* */	/* A comment */
Print() Debugging	✓	$display
Line Comments	✓	//	// A comment
Comments	✓
Semantic Indentation	X

Feature

Supported

Token

Example

Binary Literals

✓

// ([0-9]+)|(\'b)[01]+

Integers

✓

// ([0-9]+)|(\'d)[0-9]+

Floats

✓

// (\d+\.\d*|\.\d+|\d+)[eE][+-]?\d+[lL]?

Hexadecimals

✓

// ([0-9]+)|(\'h)[0-9a-fA-F]+

Octals

✓

// ([0-9]+)|(\'o)[0-7]+

✓

✓

✓

✓

✓

"Hello world"

MultiLine Comments

✓

/* */

/* A comment
*/

Print() Debugging

✓

$display

Line Comments

✓

// A comment

Comments

✓

Semantic Indentation

title	author	year	reviews	ratings	rating
HDL Programming Fundamentals: VHDL and Verilog [With CD-ROM]	Nazeih M. Botros	2005	5	55	4.15
Programming Fpgas: Getting Started with Verilog	Simon Monk		2	9	3.89
Computer Arithmetic And Verilog Hdl Fundamentals	Joseph Cavanagh	2009	1	10	4.70

title

author

year

reviews

ratings

rating

HDL Programming Fundamentals: VHDL and Verilog [With CD-ROM]

Nazeih M. Botros

2005

4.15

Programming Fpgas: Getting Started with Verilog

Simon Monk

3.89

Computer Arithmetic And Verilog Hdl Fundamentals

Joseph Cavanagh

2009

4.70

title	authors	year	publisher
Programming FPGAs: Getting Started with Verilog	Monk, Simon	2016	McGraw Hill TAB
Verilog Styles for Synthesis of Digital Systems	Smith, David R and Franzon, Paul D	2019	Pearson
Verilog HDL: Digital Design and Modeling	Cavanagh, Joseph	2007	CRC Press
The Complete Verilog Book	Sagdeo, Vivek	1998	Springer
HDL Programming Fundamentals: VHDL and Verilog (DaVinci Engineering)	Botros, Nazeih M	2005	Charles River Media
Designing Digital Computer Systems with Verilog	Lilja, David J. and Sapatnekar, Sachin S.	2007	Cambridge University Press
The Verilog PLI Handbook	Stuart Sutherland	20130418	Springer Nature
Programming FPGAs: Getting Started with Verilog	Monk, Simon	2016	McGraw Hill TAB
Digital System Design with FPGA: Implementation Using Verilog and VHDL	Unsalan, Cem and Tar, Bora	2017	McGraw-Hill Education
Verilog HDL	Palnitkar, Samir	1996	Prentice Hall PTR
Digital Logic: With an Introduction to Verilog and FPGA-Based Design	Rafiquzzaman, M. and McNinch, Steven A.	2019	Wiley
Digital Logic: With an Introduction to Verilog and FPGA-Based Design	Rafiquzzaman, M. and McNinch, Steven A.	2019	Wiley
Verilog Digital Computer Design: Algorithms into Hardware	Arnold, Mark Gordon	1998	Pearson College Div
A Verilog HDL Primer, Second Edition	Bhasker, J.	1999	Star Galaxy Pub
The Verilog PLI Handbook: A User’s Guide and Comprehensive Reference on the Verilog Programming Language Interface (The Springer International Series in Engineering and Computer Science (666))	Sutherland, Stuart	2002	Springer
Principles of Verilog PLI	Mittra, Swapnajit	1999	Springer
The Verilog PLI Handbook: A User's Guide and Comprehensive Reference on the Verilog Programming Language Interface	Sutherland, Stuart	1999	Springer
The Verilog PLI Handbook: A User’s Guide and Comprehensive Reference on the Verilog Programming Language Interface (The Springer International Series in Engineering and Computer Science (666))	Sutherland, Stuart	2013-04-18T00:00:01Z	Springer
The Verilog PLI Handbook: A User’s Guide and Comprehensive Reference on the Verilog Programming Language Interface	Sutherland, Stuart	2012	Springer
Dual Core RISC Processor with configurable hardware using VERILOG	Kumar, Nishant and Aggrawal, Ekta	2015	LAP LAMBERT Academic Publishing
Verilog Design of a Pedestrian Crossing: Verilog Programming	Gondhalekar, Ninad	2014	GRIN Publishing
A HDL & Verilog Code: Simulated Output	Sudhan, Manu and S., Manjunatha	2012	LAP LAMBERT Academic Publishing
The Verilog PLI Handbook: A User's Guide and Comprehensive Reference on the Verilog Programming Language Interface	Sutherland, Stuart	2011-10-08T00:00:01Z	Springer
HDL Programming Fundamentals: VHDL and Verilog (Davinci Engineering)	Botros	2021	Cengage Learning
Verilog Designer's Library	Bob Zeidman	1999	Pearson Education
The Verilog PLI Handbook	Stuart Sutherland	20060418	Springer Nature
Principles of Verilog PLI	Swapnajit Mittra	20121206	Springer Nature
FPGA Prototyping by Verilog Examples	Pong P. Chu	2011-09-20	Wiley
HDL with Digital Design VHDL and Verilog	Nazeih Botros	03/2015	Mercury Learning and Information
Digital VLSI Design and Simulation with Verilog	Suman Lata Tripathi and Sobhit Saxena and Sanjeet K. Sinha and Govind S. Patel	2021-12-10	Wiley
Verilog Digital System Design: RT Level Synthesis, Testbench and Verification	Zainalabedin Navabi	2005	McGraw-Hill Professional Publishing

title

authors

year

publisher

Programming FPGAs: Getting Started with Verilog

Monk, Simon

2016

McGraw Hill TAB

Verilog Styles for Synthesis of Digital Systems

Smith, David R and Franzon, Paul D

2019

Pearson

Verilog HDL: Digital Design and Modeling

Cavanagh, Joseph

2007

CRC Press

The Complete Verilog Book

Sagdeo, Vivek

1998

Springer

HDL Programming Fundamentals: VHDL and Verilog (DaVinci Engineering)

Botros, Nazeih M

2005

Charles River Media

Designing Digital Computer Systems with Verilog

Lilja, David J. and Sapatnekar, Sachin S.

2007

Cambridge University Press

The Verilog PLI Handbook

Stuart Sutherland

20130418

Springer Nature

Programming FPGAs: Getting Started with Verilog

Monk, Simon

2016

McGraw Hill TAB

Digital System Design with FPGA: Implementation Using Verilog and VHDL

Unsalan, Cem and Tar, Bora

2017

McGraw-Hill Education

Verilog HDL

Palnitkar, Samir

1996

Prentice Hall PTR

Digital Logic: With an Introduction to Verilog and FPGA-Based Design

Rafiquzzaman, M. and McNinch, Steven A.

2019

Wiley

Digital Logic: With an Introduction to Verilog and FPGA-Based Design

Rafiquzzaman, M. and McNinch, Steven A.

2019

Wiley

Verilog Digital Computer Design: Algorithms into Hardware

Arnold, Mark Gordon

1998

Pearson College Div

A Verilog HDL Primer, Second Edition

Bhasker, J.

1999

Star Galaxy Pub

The Verilog PLI Handbook: A User’s Guide and Comprehensive Reference on the Verilog Programming Language Interface (The Springer International Series in Engineering and Computer Science (666))

Sutherland, Stuart

2002

Springer

Principles of Verilog PLI

Mittra, Swapnajit

1999

Springer

The Verilog PLI Handbook: A User's Guide and Comprehensive Reference on the Verilog Programming Language Interface

Sutherland, Stuart

1999

Springer

The Verilog PLI Handbook: A User’s Guide and Comprehensive Reference on the Verilog Programming Language Interface (The Springer International Series in Engineering and Computer Science (666))

Sutherland, Stuart

2013-04-18T00:00:01Z

Springer

The Verilog PLI Handbook: A User’s Guide and Comprehensive Reference on the Verilog Programming Language Interface

Sutherland, Stuart

2012

Springer

Dual Core RISC Processor with configurable hardware using VERILOG

Kumar, Nishant and Aggrawal, Ekta

2015

LAP LAMBERT Academic Publishing

Verilog Design of a Pedestrian Crossing: Verilog Programming

Gondhalekar, Ninad

2014

GRIN Publishing

A HDL & Verilog Code: Simulated Output

Sudhan, Manu and S., Manjunatha

2012

LAP LAMBERT Academic Publishing

The Verilog PLI Handbook: A User's Guide and Comprehensive Reference on the Verilog Programming Language Interface

Sutherland, Stuart

2011-10-08T00:00:01Z

Springer

HDL Programming Fundamentals: VHDL and Verilog (Davinci Engineering)

Botros

2021

Cengage Learning

Verilog Designer's Library

Bob Zeidman

1999

Pearson Education

The Verilog PLI Handbook

Stuart Sutherland

20060418

Springer Nature

Principles of Verilog PLI

Swapnajit Mittra

20121206

Springer Nature

FPGA Prototyping by Verilog Examples

Pong P. Chu

2011-09-20

Wiley

HDL with Digital Design VHDL and Verilog

Nazeih Botros

03/2015

Mercury Learning and Information

Digital VLSI Design and Simulation with Verilog

Suman Lata Tripathi and Sobhit Saxena and Sanjeet K. Sinha and Govind S. Patel

2021-12-10

Wiley

Verilog Digital System Design: RT Level Synthesis, Testbench and Verification

Zainalabedin Navabi

2005

McGraw-Hill Professional Publishing

title	authors	year	citations	influentialCitations
Verilog HDL	S. Palnitkar	2003	60	7
Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction	Arash Saifhashemi and H. Pedram	2003	50	1
The Verilog PLI Handbook	S. Sutherland	1999	37	4
The Verilog Procedural Interface for the Verilog Hardware Description Language	C. Dawson and S. Pattanam and D. Roberts	1996	26	2
An animatable operational semantics of the Verilog hardware description language	Jonathan P. Bowen and Jifeng He and Qiwen Xu	2000	25	0
Verischemelog: Verilog embedded in Scheme	J. Jennings and Eric Beuscher	1999	21	1
An Algebraic Approach to the VERILOG Programming	H. Jifeng	2003	11	0
GCC2Verilog Compiler Toolset for Complete Translation of C Programming Language into Verilog HDL	Giang Nguyen Thi Huong and S. Kim	2011	11	0
FBDtoVerilog 2.0: An Automatic Translation of FBD into Verilog to Develop FPGA	Dong-Ah Lee and Eui-Sub Kim and Junbeom Yoo and Jang-Soo Lee and J. Choi	2014	10	0
Combining Operational Semantics, Logic Programming and Literate Programming in the Specification and Animation of the Verilog Hardware Description Language	Jonathan P. Bowen	2000	10	0
Verilog plus C language modeling with PLI 2.0: The next generation simulation language	S. Meyer	1998	6	0
The PowerPC 603 C++ Verilog interface model	R. P. Voith	1994	5	0
Faster Verilog simulations using a cycle based programming methodology	M. Becker	1996	5	1
DAVE: Deriving Automatically Verilog from English	H. Pearce and Benjamin Tan and R. Karri	2020	3	1
Introduction to Verilog	T. R. Padmanabhan and B. T. Sundari	2004	1	0
Principles of Verilog PLI	S. Mittra	2012	1	1
FeatureVerilog: Extending Verilog to Support Feature-Oriented Programming	Jun Ye and QingPing Tan and Tun Li and GuoRong Cao	2011	1	0
Comparative Analysis between Verilog and Chisel in RISC-V Core Design and Verification	Jaekyung Im and Seokhyeong Kang	2021	1	0

title

authors

year

citations

influentialCitations

Verilog HDL

S. Palnitkar

2003

Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction

Arash Saifhashemi and H. Pedram

2003

The Verilog PLI Handbook