Keywords in SystemVerilog

accepton alias always alwayscomb alwaysff alwayslatch and assert assign assume automatic before begin bind bins binsof bit break buf bufif0 bufif1 byte case casex casez cell chandle checker class clocking cmos config const constraint context continue cover covergroup coverpoint cross deassign default defparam design disable dist do edge else end endcase endchecker endclass endclocking endconfig endfunction endgenerate endgroup endinterface endmodule endpackage endprimitive endprogram endproperty endspecify endsequence endtable endtask enum event eventually expect export extends extern final firstmatch for force foreach forever fork forkjoin function generate genvar global highz0 highz1 if iff ifnone ignorebins illegalbins implements implies import incdir include initial inout input inside instance int integer interconnect interface intersect join joinany joinnone large let liblist library local localparam logic longint macromodule matches medium modport module nand negedge nettype new nexttime nmos nor noshowcancelled not notif0 notif1 null or output package packed parameter pmos posedge primitive priority program property protected pull0 pull1 pulldown pullup pulsestyleondetect pulsestyleonevent pure rand randc randcase randsequence rcmos real realtime ref reg rejecton release repeat restrict return rnmos rpmos rtran rtranif0 rtranif1 salways seventually snexttime suntil suntilwith scalared sequence shortint shortreal showcancelled signed small soft solve specify specparam static string strong strong0 strong1 struct super supply0 supply1 syncaccepton syncrejecton table tagged task this throughout time timeprecision timeunit tran tranif0 tranif1 tri tri0 tri1 triand trior trireg type typedef union unique unique0 unsigned until untilwith untyped use uwire var vectored virtual void wait waitorder wand weak weak0 weak1 while wildcard wire with within wor xnor xor