VHDL, aka VHSIC Hardware Description Language, is a hardware description language created in 1983.
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VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.. Read more on Wikipedia...
use std.textio.all; entity hello_world is end hello_world; architecture behaviour of hello_world is begin process begin write (output, String'("Hello World")); wait; end process; end behaviour;
--Hello World in VHDL ENTITY helloworld IS END helloworld; ARCHITECTURE hw OF helloworld IS BEGIN ASSERT FALSE REPORT "HELLO, WORLD!" SEVERITY NOTE; END hw;
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
process begin wait until START = '1'; -- wait until START is high for i in 1 to 10 loop -- then wait for a few clock periods... wait until rising_edge(CLK); end loop; for i in 1 to 10 loop -- write numbers 1 to 10 to DATA, 1 every cycle DATA <= to_unsigned(i, 8); wait until rising_edge(CLK); end loop; -- wait until the output changes wait on RESULT; -- now raise ACK for clock period ACK <= '1'; wait until rising_edge(CLK); ACK <= '0'; -- and so on... end process;
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