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VHDL

VHDL

VHDL, aka VHSIC Hardware Description Language, is a hardware description language created in 1983.

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VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.. Read more on Wikipedia...


Example from hello-world:
use std.textio.all; entity hello_world is end hello_world; architecture behaviour of hello_world is begin process begin write (output, String'("Hello World")); wait; end process; end behaviour;
Example from the Hello World Collection:
--Hello World in VHDL ENTITY helloworld IS END helloworld; ARCHITECTURE hw OF helloworld IS BEGIN ASSERT FALSE REPORT "HELLO, WORLD!" SEVERITY NOTE; END hw;
Example from Linguist:
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
Example from Wikipedia:
process begin wait until START = '1'; -- wait until START is high for i in 1 to 10 loop -- then wait for a few clock periods... wait until rising_edge(CLK); end loop; for i in 1 to 10 loop -- write numbers 1 to 10 to DATA, 1 every cycle DATA <= to_unsigned(i, 8); wait until rising_edge(CLK); end loop; -- wait until the output changes wait on RESULT; -- now raise ACK for clock period ACK <= '1'; wait until rising_edge(CLK); ACK <= '0'; -- and so on... end process;

Keywords in VHDL

abs access after alias all and architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic group guarded if impure in inertial inout is label library linkage literal loop map mod nand new next nor not null of on open or others out package port postponed procedure process pure range record register reject rem report return rol ror select severity signal shared sla sll sra srl subtype then to transport type unaffected units until use variable wait when while with xnor xor

Language features

Feature Supported Example Token
Binary Literals
-- B"[01_]+"
Integers
-- \d{1,2}#[0-9a-f_]+#?
Floats
-- (\d+\.\d*|\.\d+|\d+)E[+-]?\d+
Hexadecimals
-- X"[0-9a-f_]+"
Octals
-- O"[0-7_]+"
Conditionals
Functions
While Loops
Strings
"Hello world"
"
Print() Debugging write
Line Comments
-- A comment
--
Comments
Semantic Indentation ϴ
MultiLine Comments ϴ

Books about VHDL on goodreads

title author year reviews ratings rating
HDL Programming Fundamentals: VHDL and Verilog [With CD-ROM] Nazeih M. Botros 2005 5 55 4.15
VHDL: Programming by Example [With CDROM] Douglas L. Perry 1990 1 14 3.36
VHDL for Engineers Kenneth L. Short 2008 0 5 4.00

Books about VHDL from ISBNdb

title authors year publisher
Digital Fundamentals with VHDL Floyd, Thomas L. 2002 Prentice Hall
Digital Systems Design Using VHDL Roth, Jr. Charles H. and John, Lizy K. 2007 Cengage Learning
VHDL for Engineers Short, Kenneth 2008 Pearson
Vhdl Edition (Computer Engineering Series) Perry, Douglas 1993 Mcgraw-hill Inc
HDL Programming Fundamentals: VHDL and Verilog (DaVinci Engineering) Botros, Nazeih M 2005 Charles River Media
VHDL Design Representation and Synthesis (2nd Edition) Armstrong, James R. and Gray, F. Gail 2000 Prentice Hall
VHDL for Simulation, Synthesis and Formal Proofs of Hardware (The Springer International Series in Engineering and Computer Science, 183) 1992 Springer
Digital Logic Simulation And Cpld Programming With Vhdl Steve Waterman 2002 Prentice Hall
The VHDL Reference: A Practical Guide to Computer-Aided Integrated Circuit Design including VHDL-AMS Ulrich Heinkel and Werner Haas and Martin Padeffke and Thomas Buerner and Herbert Braisz 2000 Wiley, John & Sons, Incorporated
Digital System Design with FPGA: Implementation Using Verilog and VHDL Unsalan, Cem and Tar, Bora 2017 McGraw-Hill Education
The Designer's Guide to VHDL (ISSN) Ashenden, Peter J. 2010 Morgan Kaufmann
Digital Systems Design with VHDL and Synthesis: An Integrated Approach Chang, K. C. 1999 Wiley-IEEE Computer Society Pr
VHDL : Programming By Example Perry, Douglas 2002 McGraw-Hill Education
Fundamentals of Digital Logic with VHDL Design Brown, Stephen D. 2008 McGraw-Hill College
Digital Electronics and Design with VHDL Pedroni, Volnei A. 2008 Morgan Kaufmann
A Tutorial Introduction to VHDL Programming Gazi, Orhan 2018 Springer
VHDL 2008: Just the New Stuff (Systems on Silicon) Ashenden, Peter J. and Lewis, Jim 2007 Morgan Kaufmann
Digital System Design with VHDL (2nd Edition) Zwolinski, Mark 2003 Pearson
Digital Electronics and Design with VHDL Pedroni Ph.D. California Institute of Technology; former visiting Professor Harvey Mudd College, Volnei A. 2008 Morgan Kaufmann
Vhdl Starter's Guide Yalamanchili, Sudhakar 1997 Prentice Hall
A Tutorial Introduction to VHDL Programming Gazi, Orhan 2018 Springer
Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL Ferdjallah, Mohammed 2011 Wiley
HDL Programming Fundamentals: VHDL and Verilog, w/CD NAZEIH M.BOTROS 1708 Wiley India Private Limited
VHDL for Logic Synthesis Rushton, Andrew 1998 Wiley
Digital System Design and VHDL Zwolinski, Mark 2000 Prentice Hall
Design of a Data Analyser for Ethernet Packets Using VHDL: Analysis and Representation of Ethernet Communication Protocol Using Finite State Machines with VHDL Programming Gooroochurn, Mahendra 2016 LAP LAMBERT Academic Publishing
VHDL and FPLDs in Digital Systems Design, Prototyping and Customization Salcic, Zoran 2012 Springer
A Tutorial Introduction to VHDL Programming Gazi, Orhan 2019 Springer
HDL Programming Fundamentals: VHDL and Verilog (Davinci Engineering) Botros 2021 Cengage Learning
Vhdl Programming L. Baker John Wiley & Sons Inc
VHDL Programming Syed Zaheeruddin and Baddiri Narsimha and Pudari Chiranjeevi 2019-07-24 LAP LAMBERT Academic Publishing
Kompaktkurs VHDL Paul Molitor; Jörg Ritter 20130128 De Gruyter
Prozessorentwurf mit VHDL Dieter Wecker 20180611 De Gruyter
Vhdl For Engineers Kenneth L. Short 2011 Pearson Higher Ed
A Guide To Vhdl Patricia Langstraat; Stanley Mazor 2010 Springer
Digital Electronics With Vhdl Programming Brian Hemmelman 2001 Prentice Hall
The Designer's Guide To Vhdl Peter J. Ashenden 2001 Elsevier
Digital Systems Design Using VHDL Charles H. Roth, Jr.; Lizy K. John 20070330 Cengage Learning US
A Tutorial Introduction to VHDL Programming Orhan Gazi 2018-08-18 Springer
VHDL A Complete Guide - 2021 Edition Gerardus Blokdyk 2020 Emereo
VHDL based automated solar panel intensity controller Beenish Habib and Rameesa Mufti 2019-03-10 LAP LAMBERT Academic Publishing
HDL with Digital Design VHDL and Verilog Nazeih Botros 03/2015 Mercury Learning and Information
Fundamentals of Digital and Computer Design with VHDL Sandige, Richard; Sandige, Michael 01/2012 McGraw-Hill Higher Education (US)
Vhdl Programming With Advanced Topics (wiley Professional Computing) Louis Baker 1993 Wiley
Formal Semantics and Proof Techniques for Optimizing VHDL Models Kothanda Umamageswaran and Sheetanshu L. Pandey and Philip A. Wilsey 2012 Springer-Verlag New York, LLC
Contemporary Logic Design 32703 And Vhdl For Programming Logic Package Katz 1998 Not Avail
Design Automation. Behavioural Languages. Vhdl Multilogic System For Model Interoperability British Standards Institute Staff 2002

Publications about VHDL from Semantic Scholar

title authors year citations influentialCitations
HML, a novel hardware description language and its translation to VHDL Yanbing Li and M. Leeser 2000 53 5
A Guide to VHDL S. Mazor and Patricia Langstraat 1992 48 2
HML: an innovative hardware description language and its translation to VHDL Yanbing Li and M. Leeser 1995 36 6
VHDL Descriptions for the FPGA Implementation of PWL-Function-Based Multi-Scroll Chaotic Oscillators E. Tlelo-Cuautle and A. Quintas-Valles and L. G. de la Fraga and J. Rangel-Magdaleno 2016 26 0
A simple denotational semantics, proof theory and a validation condition generator for unit-delay VHDL Peter T. Breuer and Luis Sánchez-Fernández and C. D. Kloos 1995 22 2
A VHDL compiler based on attribute grammar methodology Rodney Farrow and A. Stanculescu 1989 19 0
A refinement calculus for the synthesis of verified hardware descriptions in VHDL Peter T. Breuer and C. D. Kloos and Andrés Marín López and N. M. Madrid and Luis Sánchez-Fernández 1997 18 1
An educational environment for VHDL hardware description language using the WWW and specific workbench A. Etxebarria and I. Oleagordía and M. Sanchez 2001 17 0
VHDL Standards P. Ashenden 2001 15 1
Fuzzy logic controller implementation on a FPGA using VHDL Davi Nunes Oliveira and Arthur Plínio De Souza Braga and Otacílio da Mota Almeida 2010 14 1
Denotational semantics of a synchronous VHDL subset D. Borrione and A. Salem 1995 11 0
Source level optimisation of VHDL for behavioural synthesis T.P.K. Nijhar and A. D. Brown 1997 11 1
Transformation of VHDL descriptions into DEVS models for fault modeling L. Capocchi and F. Bernardi and D. Federici and P. Bisgambiglia 2003 11 0
Design and implementation of a Mamdani Fuzzy Inference System on an FPGA using VHDL Davi Nunes Oliveira and Gustavo Alves de Lima Henn and Otacílio da Mota Almeida 2010 10 0
Design of FPGA based 8-bit RISC controller IP core using VHDL R. P. Aneesh and K. Jiju 2012 10 0
A plug-in to Eclipse for VHDL source codes: functionalities B. Niton and K. Pozniak and R. Romaniuk 2012 10 0
VHDL Critique J. Nash and Larry F. Saunders 1986 8 0
VHDL implementation of IEEE 754 floating point unit Anjana Sasidharan and P. Nagarajan 2014 8 1
Application of VHDL to software radio technology J. Mccloskey 1998 7 0
Automatic generation of VHDL code from traditional ladder diagrams applying a model-driven engineering approach D. Alonso and J. Suardíaz and P. Navarro and P. Alcover and J.A. Lopez 2009 6 0
C to VHDL compiler Piotr P. Berdychowski and Wojciech Zabolotny 2010 6 0
VHDL models e-assessment in Moodle environment K. Jelemenska and P. Cicak and M. Gazik 2016 6 0
ADVISE. Performance evaluation of parallel VHDL simulation Wilco Van Hoogstraeten and H. Corporaal 1997 5 0
Combining Software and Hardware Test Generation Methods to Verify VHDL Models V. Jusas and Tomas Neverdauskas 2013 5 0
VHDL Design and Synthesis of 64 bit RISC Processor System on Chip (SoC) Navneet Kaur 2013 5 1
Designing Digital Systems Using Cartesian Genetic Programming and VHDL B. Henson and James Alfred Walker and M. Trefzer and A. Tyrrell 2018 5 0
VHDL Implementation of a (255,191) Reed Solomon Coder for DVB-H M. Mehnert and D.F. von Droste and D. Schiel 2006 4 0
FPGA implementation of RS codec with interleaver in DVB-T using VHDL Sara Kamar and Abdelmoniem Fouda and A. Zekry and Abdelmoniem Elmahdy 2017 4 0
Incremental Design—Application of a Software-based Method for High-level Hardware Design with VHDL A. Hohl 1992 3 0
Modeling digital systems using VHDL P. Ashenden 1998 3 0
VHDL based circuits design and synthesis on FPGA: A dice game example for education Sarah Toonsi and Miznan G. Behri and S. Qaisar and Enas Melibari and Sarah Alolyan 2017 3 0
A Small, Effective Vhdl Subset For The Digital Systems Course P. Chu 2004 2 0
Design and Implementation of ARP Functionality Based on VHDL Liu Tian-hua and Zhu Hong-feng and Liu Jun and Zhou Chuan-sheng and Chang Gui-ran 2006 2 0
Diseño de un codificador y decodificador digital Reed-Solomon usando programación en VHDL C. Sandoval and A. Fedón 2011 2 0
Adaptive microphone array beamforming for teleconferencing using VHDL and parallel architectures Tony P. W. Price and D. Howard and A. Lewis and A. Tyrrell 1999 1 0
Switch-Level Modeling in VHDL A. Stanculescu 1991 1 0
Novel Method to Generate Tests for VHDL V. Jusas and Tomas Neverdauskas 2013 1 0
FBDtoVHDL: An Automatic Translation from FBD into VHDL for FPGA Development Jaeyeob Kim and Eui-Sub Kim and Junbeom Yoo and Young Jun Lee and J. Choi 2016 1 0
Electronic Circuit and System Design using Python and VHDL I. Grout 2018 1 0
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